Preliminary Design
Wavelan Device Interface
The Wavelan device we will be using is controlled by a Prism MAC
Controller by Intersil. A host driver communicates with the Prism MAC
through a set of Interface Registers, which are I/O adresses used to
transfer commands and data.
An I/O offset is assigned to each register. All registers are 16 Bits, but
two I/O ports are used for each registers. The registers are organized in
the following groups:
- Command Status Registers
- FID Management Registers
- Buffer Access Path
- Event Registers
- Control Registers
- Host Software Registers
Register Access
The access to the MAC registers will be encapsulated in a class that
provides memory mapping, reading and writing. This device driver will
access the registers through this class.
Device Driver
The Device Driver will provide access to the device, including send and
receive methods, transmission parameter settings, etc.
The MAC send/receive protocols that will be implemented are specified in
the following figures:
