ML403
From TheUbberCannon
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About
The ML401/ML402/ML403 evaluation platform enables designers to investigate and experiment with features of the VirtexTM-4 family of FPGAs.
It features 64-MB DDR SDRAM, 32-bit interface running up to 266-MHz data rate, various external clock/ocillators connectors, LEDs and buttons, audio input and output codec (AC/97), connectors (as RS232), a LCD (16 x 2 characters), one 4 Kb IIC EEPROM, and some others busses, expansions and connectors (see Links->Manual for more).
To this exercise RS232, LCD and some expansion pins will be required for its completion. Of course the board's main processor and the FPGA will be used also.
Main Processor
A PowerPC405 Embedded Processor
FPGA
REF: XC4VFX12-FF668-10
LCD Display
Lumex LCM-S01602DTR/M
By the pin assignement, appear to be a Hitachi HD44780 LCD controller based LCD display, setted to 4bit operation mode.
Serial Interfaces
We must find a way to allow EPOS to use 2 UARTs.
