EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
0GLB fpga_0_SRAM_CLOCK O 1 sys_clk_s
1A fpga_0_DDR_SDRAM_64Mx32_DDR_DQS_pin IO 0:3 fpga_0_DDR_SDRAM_64Mx32_DDR_DQS
2A fpga_0_DDR_SDRAM_64Mx32_DDR_DQ_pin IO 0:31 fpga_0_DDR_SDRAM_64Mx32_DDR_DQ
3A fpga_0_DDR_SDRAM_64Mx32_DDR_Addr_pin O 0:12 fpga_0_DDR_SDRAM_64Mx32_DDR_Addr
4A fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr_pin O 0:1 fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr
5A fpga_0_DDR_SDRAM_64Mx32_DDR_CASn_pin O 1 fpga_0_DDR_SDRAM_64Mx32_DDR_CASn
6A fpga_0_DDR_SDRAM_64Mx32_DDR_CKE_pin O 1 fpga_0_DDR_SDRAM_64Mx32_DDR_CKE
7A fpga_0_DDR_SDRAM_64Mx32_DDR_CSn_pin O 1 fpga_0_DDR_SDRAM_64Mx32_DDR_CSn
8A fpga_0_DDR_SDRAM_64Mx32_DDR_Clk_pin O 1 fpga_0_DDR_SDRAM_64Mx32_DDR_Clk
9A fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn_pin O 1 fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn
10A fpga_0_DDR_SDRAM_64Mx32_DDR_DM_pin O 0:3 fpga_0_DDR_SDRAM_64Mx32_DDR_DM
11A fpga_0_DDR_SDRAM_64Mx32_DDR_RASn_pin O 1 fpga_0_DDR_SDRAM_64Mx32_DDR_RASn
12A fpga_0_DDR_SDRAM_64Mx32_DDR_WEn_pin O 1 fpga_0_DDR_SDRAM_64Mx32_DDR_WEn
13B fpga_0_LEDs_4Bit_GPIO_IO_pin IO 0:3 fpga_0_LEDs_4Bit_GPIO_IO
14C fpga_0_LEDs_Positions_GPIO_IO_pin IO 0:4 fpga_0_LEDs_Positions_GPIO_IO
15D fpga_0_Push_Buttons_Position_GPIO_IO_pin IO 0:4 fpga_0_Push_Buttons_Position_GPIO_IO
16E fpga_0_RS232_Uart_0_sin_pin I 1 fpga_0_RS232_Uart_0_sin
 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
17E fpga_0_RS232_Uart_0_sout_pin O 1 fpga_0_RS232_Uart_0_sout
18F fpga_0_RS232_Uart_1_sin_pin I 1 fpga_0_RS232_Uart_1_sin
19F fpga_0_RS232_Uart_1_sout_pin O 1 fpga_0_RS232_Uart_1_sout
20G fpga_0_RS232_Uart_2_sin_pin I 1 fpga_0_RS232_Uart_2_sin
21G fpga_0_RS232_Uart_2_sout_pin O 1 fpga_0_RS232_Uart_2_sout
22H fpga_0_SRAM_256Kx32_Mem_DQ_pin IO 0:31 fpga_0_SRAM_256Kx32_Mem_DQ
23H fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin O 1 fpga_0_SRAM_256Kx32_Mem_ADV_LDN
24H fpga_0_SRAM_256Kx32_Mem_BEN_pin O 0:3 fpga_0_SRAM_256Kx32_Mem_BEN
25H fpga_0_SRAM_256Kx32_Mem_CEN_pin O 0:0 fpga_0_SRAM_256Kx32_Mem_CEN
26H fpga_0_SRAM_256Kx32_Mem_OEN_pin O 0:0 fpga_0_SRAM_256Kx32_Mem_OEN
27H fpga_0_SRAM_256Kx32_Mem_WEN_pin O 1 fpga_0_SRAM_256Kx32_Mem_WEN
28I fpga_0_SRAM_256Kx32_Mem_A_pin O 9:29 fpga_0_SRAM_256Kx32_Mem_A
29J sys_clk_pin I 1 dcm_clk_s  CLK 
30K fpga_0_DDR_CLK_FB I 1 ddr_feedback_s  CLK 
31L gpio_char_lcd IO 0:6 gpio_char_lcd
32M sys_rst_pin I 1 sys_rst_s  RESET