Computer Architecture and Organization Group
In the context of integrated hardware and software design for dedicated systems, this research line focus on methods and tools for the development of hardware components targeting programmable logic devices (often called IP - Intellectual Property), and their integration in SoCs (System-on-a-Chip). In this group, we do research in the following topics:
- Dynamic reconfiguration;
- System-level design and validation;
- Rapid-prototyping and automatic system generation.
- Formal Verification of System Components.
In the context of cyber-physical systems, this research line focus on methods and tools for the development of hardware components based on biomolecules and living organisms, targeting biological computers and their integration to cyber components (software) and other physical components (electronics). In this group, we do research in the following topics:
- Modeling and simulation of biological systems.
- Design of execution units and microarchitectures.
- Formal verification of components.
Current Research Activities
- Unified design of embedded system components: The increasing complexity of current embedded systems applications is pushing their design to higher levels of abstraction, leading to the convergence between hardware and software development methodologies. We aim to close the gap between hardware and software design by developing a methodology that handles both domains in a unified fashion. We leverage on aspect-oriented programming(AOP) and object-oriented programming(OOP) techniques in order to provide unified C++ descriptions of components. The main goal of this research line is to define concerns specific of hardware or software and provide their encapsulation in aspect programs. By simply applying these aspect programs, the unified descriptions can be both compiled to software binaries or synthesized to dedicated hardware using high-level synthesis tools.
- Reconfigurable Computing: The time required to perform the reconfiguration of devices used in reconfigurable computing can be a limitation for some applications that require real-time service. This research track aims to find mechanisms that can guarantee the fulfillment of scheduling hybrid tasks (hardware and software) for real-time applications that are managed by an operating system.
- Digital signal processing applied on Telecommunications: The demand for voice communication via the packet switching, also known as IP telephony has increased significantly over the last decade. In addition, data applications are increasingly being associated with the telephone, a phenomenon known as Digital Convergence. The goal of this research track is to find structural alternatives and communication mechanisms for algorithms used in telecommunications so that they can deliver higher performance while minimizing deployment costs.
- Network-on-Chip solutions: Different solutions based on Network-on-Chip have been used as communication architecture for data flows the require quality of service guarantees. Some solutions are based on priority levels of the flows, while other solutions are based on the use of dedicated channels. This research track aims to find an alternative NoC architecture that can ensure quality of services for flows, keeping low silicon consumption, for a system where all flows have such requirements.
- Formal Verification of System Components: Due to intense utilization of computational systems it is growing the need that such systems to be trustful. Thus, is necessary the existence of methods to assure the development of trustworthy computational systems. It is desired that these methods could be applied since the early phases of the project of a system and is necessary that the trust properties remain valid until the final system generation and during all life cycle of the system. This research track aims to formally verify systems components described in system descriptions languages, such as SystemC and SpecC, in a agnostic way of which parts are going to be implemented on software and which parts are going to be implemented on hardware.
If you are interested in our research and want to join us, please refer to available work plans (or fell free to provide your own proposal) and send us an email.
- Cleiber Marques da Silva
- João Paulo Pizani Flor
- Leonardo Kessler Slongo
- Mario Baldini
- Tiago Rogério Mück
- Vagner Guadagnin
- Wesley Gonçalves